Electronic packages containing multiple chips are not new. Electronic packages may be classified into different ways. For example, some prior art electronic packages can be classified to include but not limited to (i) wire bonding (WB) die stacking, (ii) package-on-package or package stacking (PoP) and (iii) through-silicon-via (TSV). While these different classes of electronic packages may be advantageous in some ways, they are often deficient in others. For example, although WB die stacking may be considered relatively simple conceptually in their structure and is relatively mature as a technology their signal performance (due to the requirement of using a large amount of external wire connections), form factor and testability is generally considered to be unsatisfactory. Also, WB die stacking often results a rather bulky package which would be undesirable in compact electronic device environment. PoP may have a better testability but still their electrical performance and form factor are also not satisfactory. Prior art TSV based die stacking packages have better electrical performance and form factor but yet they suffer from poor testability and high manufacturing cost due to complications in their fabrication.
The present invention seeks to provide a type of three-dimensional electronic package which can address some if not all the above problems, or at least to provide the general public with an alternative.